So-ADE debugger knows how to browse any AST from your debug session. It displays it using a Nice Tree Viewer which enables you to dig into any level.
Understanding the structural aspect of the AST has never been as easy, especially for beginners
So-ADE debugger comes with built-in configurations for all AST from Verific (VHLD, Verilog, SystemVerilog). Using its programming interface, you can extend it to support any home made AST structures for any languages.
So-ADE debugger is equality featured for Netlist navigation. Netlist can be viewed using:
Embedded schematic viewer for even greater analysis capabilities. Your debugger is as features as most EDA tools.
So-ADE debugger comes with built-in configuration for Verific database model as well as So‑ADE graphengine own model.
So-ADE debugger has a very powerfull stack analysis tool that :
Extracts automatically from stack all netlist elements affected by a recursive algorithum
Builds the corresponding sub-schematic.
This tool makes it almost trivial to analyse and debug behavioral aspect of your program on real case.
On demand, you are able to extend the generated schematic to browse connected gates.
So-ADE debugger can generate Verilog code snippet for the resulting schematic, making it instantaneous to build sub-testcase corresponding to the currently analysed netlist pattern.
So-ADE debugger is working from any core as its functionnalities does not relies on executing callback in debugged program. You are granted to debug critical core from customer.
Release Note: here